Timeline for reverse bias of the gate of an N-channel enhancement mosfet
Current License: CC BY-SA 4.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 6, 2020 at 21:26 | vote | accept | jrive | ||
| Apr 6, 2020 at 20:21 | comment | added | G36 | Yes, it will be +6V because if the MOSFET substrate was not short together with a source (due to physical construction) it will be a fully symmetrical device. | |
| Apr 6, 2020 at 19:16 | comment | added | jrive | yep, it is obvious from that data sheet, thank you. The datasheet of the device I was looking at (a P-channel, CSD25213W10) does not specify it... Unfortunately, I can't add the pic here... It specifies it only as BVGSS Gate to Source Voltage; VDS = 0V, IG = –250μA –6.0 V (min) I asked the question in terms of an N-channel to avoid any confusion, knowing that i would understand how any given answer would apply to the p-channel device. So, although the datasheet for the CSD25213W10 does not specify the maximum reverse Vgs, it is then understood to be +6V? see updated question question.... | |
| Apr 6, 2020 at 18:11 | history | answered | G36 | CC BY-SA 4.0 |