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In order to drive a N-channel JFET into its saturation region, the following requirements must be met:

$$V_{GS} \le V_{GS(off)} $$

$$V_{DS} > V_{GS} - V_{GS(off)}$$

Plugging in your values:

$$V_{GS} \le -1.17V \rightarrow fulfilled$$

$$-7.35 > -7.4V + 1.17V=-6.23V \rightarrow unfufilled$$

NOTE: \$V_{GS(off)}=-1.17V\$ comes from the model implementation. Right click on it and you can see its properties. All the other values comes from your first simulation.

EDIT #1

Although not the most elegant solution, if you still want to use a NJFET, you have to ensure that the drain voltage of the FET is not fixed by the \$V_{FWD}\$ of the BJT. I just added some random values, and you would have to optimize it:

EDIT #2

Here is a circuit similar to the one, shown in the video. (After watching the end of the video, I am almost sure that he is using a MOSFET instead of a JFET)

How it works

As you already explained, the components \$R_G\$, \$M_1\$, \$Q1\$ and \$R_b\$ form a controlled current sink. Disregarding the upper section for the moment, once the circuit is turned on, the source voltage of the MOSFET \$M_1\$ increases until it reaches \$\approx 650mV\$, thus turning on the BJT \$Q_1\$, which provides a negative feedback, which in turn reduces the \$V_{GS}\$ of the \$M_1\$.

There are two requiremts which must be fulfilled for the current source.

$$R_b > \frac{650mV}{I_{sink}}$$

AND

$$R_b > \frac{R_t\cdot 650mV}{V_{cc}-V_Z-650mV}$$

First condition ensures that there's enough current through \$R_b\$ to turn on \$Q_1\$, whereas the second one ensures that the voltage across \$R_b\$ is large enough to turn on \$Q_1\$.

The upper section of the circuit works as follows:

During start up the zener \$D_1\$ ensures that the gate voltage of \$M_2\$ is \$\approx - V_Z = -4.7V\$. At this moment the mosfet is on, and its source voltage starts to ramp ump until its \$V_{GS} < V_{th}\$ which yields an output voltage \$V_{out}\approx -15V + 4.7V + V_{th} = -7V \$

In order to drive a N-channel JFET into its saturation region, the following requirements must be met:

$$V_{GS} \le V_{GS(off)} $$

$$V_{DS} > V_{GS} - V_{GS(off)}$$

Plugging in your values:

$$V_{GS} \le -1.17V \rightarrow fulfilled$$

$$-7.35 > -7.4V + 1.17V=-6.23V \rightarrow unfufilled$$

NOTE: \$V_{GS(off)}=-1.17V\$ comes from the model implementation. Right click on it and you can see its properties. All the other values comes from your first simulation.

EDIT #1

Although not the most elegant solution, if you still want to use a NJFET, you have to ensure that the drain voltage of the FET is not fixed by the \$V_{FWD}\$ of the BJT. I just added some random values, and you would have to optimize it:

EDIT #2

Here is a circuit similar to the one, shown in the video. (After watching the end of the video, I am almost sure that he is using a MOSFET instead of a JFET)

How it works

As you already explained, the components \$R_G\$, \$M_1\$, \$Q1\$ and \$R_b\$ form a controlled current sink. Disregarding the upper section for the moment, once the circuit is turned on, the source voltage of the MOSFET \$M_1\$ increases until it reaches \$\approx 650mV\$, thus turning on the BJT \$Q_1\$, which provides a negative feedback, which in turn reduces the \$V_{GS}\$ of the \$M_1\$.

There are two requiremts which must be fulfilled for the current source.

$$R_b > \frac{650mV}{I_{sink}}$$

AND

$$R_b > \frac{R_t\cdot 650mV}{V_{cc}-V_Z-650mV}$$

First condition ensures that there's enough current through \$R_b\$ to turn on \$Q_1\$, whereas the second one ensures that the voltage across \$R_b\$ is large enough to turn on \$Q_1\$.

The upper section of the circuit works as follows:

During start up the zener \$D_1\$ ensures that the gate voltage of \$M_2\$ is \$\approx - V_Z = -4.7V\$. At this moment the mosfet is on, and its source voltage starts to ramp ump until its \$V_{GS} < V_{th}\$ which yields an output voltage \$V_{out}\approx -4.7V - V_{th} = -7V \$

In order to drive a N-channel JFET into its saturation region, the following requirements must be met:

$$V_{GS} \le V_{GS(off)} $$

$$V_{DS} > V_{GS} - V_{GS(off)}$$

Plugging in your values:

$$V_{GS} \le -1.17V \rightarrow fulfilled$$

$$-7.35 > -7.4V + 1.17V=-6.23V \rightarrow unfufilled$$

NOTE: \$V_{GS(off)}=-1.17V\$ comes from the model implementation. Right click on it and you can see its properties. All the other values comes from your first simulation.

EDIT #1

Although not the most elegant solution, if you still want to use a NJFET, you have to ensure that the drain voltage of the FET is not fixed by the \$V_{FWD}\$ of the BJT. I just added some random values, and you would have to optimize it:

EDIT #2

Here is a circuit similar to the one, shown in the video. (After watching the end of the video, I almost sure that he is using a MOSFET instead of a JFET)

How it works

As you already explained, the components \$R_G\$, \$M_1\$, \$Q1\$ and \$R_b\$ form a controlled current sink. Disregarding the upper section for the moment, once the circuit is turned on, the source voltage of the MOSFET \$M_1\$ increases until it reaches \$\approx 650mV\$, thus turning on the BJT \$Q_1\$, which provides a negative feedback, which in turn reduces the \$V_{GS}\$ of the \$M_1\$.

There are two requiremts which must be fulfilled for the current source.

$$R_b > \frac{650mV}{I_{sink}}$$

AND

$$R_b > \frac{R_t\cdot 650mV}{V_{cc}-V_Z-650mV}$$

First condition ensures that there's enough current through \$R_b\$ to turn on \$Q_1\$, whereas the second one ensures that the voltage across \$R_b\$ is large enough to turn on \$Q_1\$.

The upper section of the circuit works as follows:

During start up the zener \$D_1\$ ensures that the gate voltage of \$M_2\$ is \$\approx - V_Z = -4.7V\$. At this moment the mosfet is on, and its source voltage starts to ramp ump until its \$V_{GS} < V_{th}\$ which yields an output voltage \$V_{out}\approx -15V + 4.7V + V_{th} = -7V \$

In order to drive a N-channel JFET into its saturation region, the following requirements must be met:

$$V_{GS} \le V_{GS(off)} $$

$$V_{DS} > V_{GS} - V_{GS(off)}$$

Plugging in your values:

$$V_{GS} \le -1.17V \rightarrow fulfilled$$

$$-7.35 > -7.4V + 1.17V=-6.23V \rightarrow unfufilled$$

NOTE: \$V_{GS(off)}=-1.17V\$ comes from the model implementation. Right click on it and you can see its properties. All the other values comes from your first simulation.

EDIT #1

Although not the most elegant solution, if you still want to use a NJFET, you have to ensure that the drain voltage of the FET is not fixed by the \$V_{FWD}\$ of the BJT. I just added some random values, and you would have to optimize it:

EDIT #2

Here is a circuit similar to the one, shown in the video. (After watching the end of the video, I am almost sure that he is using a MOSFET instead of a JFET)

How it works

As you already explained, the components \$R_G\$, \$M_1\$, \$Q1\$ and \$R_b\$ form a controlled current sink. Disregarding the upper section for the moment, once the circuit is turned on, the source voltage of the MOSFET \$M_1\$ increases until it reaches \$\approx 650mV\$, thus turning on the BJT \$Q_1\$, which provides a negative feedback, which in turn reduces the \$V_{GS}\$ of the \$M_1\$.

There are two requiremts which must be fulfilled for the current source.

$$R_b > \frac{650mV}{I_{sink}}$$

AND

$$R_b > \frac{R_t\cdot 650mV}{V_{cc}-V_Z-650mV}$$

First condition ensures that there's enough current through \$R_b\$ to turn on \$Q_1\$, whereas the second one ensures that the voltage across \$R_b\$ is large enough to turn on \$Q_1\$.

The upper section of the circuit works as follows:

During start up the zener \$D_1\$ ensures that the gate voltage of \$M_2\$ is \$\approx - V_Z = -4.7V\$. At this moment the mosfet is on, and its source voltage starts to ramp ump until its \$V_{GS} < V_{th}\$ which yields an output voltage \$V_{out}\approx -15V + 4.7V + V_{th} = -7V \$

In order to drive a N-channel JFET into its saturation region, the following requirements must be met:

$$V_{GS} \le V_{GS(off)} $$

$$V_{DS} > V_{GS} - V_{GS(off)}$$

Plugging in your values:

$$V_{GS} \le -1.17V \rightarrow fulfilled$$

$$-7.35 > -7.4V + 1.17V=-6.23V \rightarrow unfufilled$$

NOTE: \$V_{GS(off)}=-1.17V\$ comes from the model implementation. Right click on it and you can see its properties. All the other values comes from your first simulation.

You could replace the JFET with a NMOSFET, and the negative feedback idea you already explained still holds true:

EDIT #1

Although not the most elegant solution, if you still want to use a NJFET, you have to ensure that the drain voltage of the FET is not fixed by the \$V_{FWD}\$ of the BJT. I just added some random values, and you would have to optimize it:

In order to drive a N-channel JFET into its saturation region, the following requirements must be met:

$$V_{GS} \le V_{GS(off)} $$

$$V_{DS} > V_{GS} - V_{GS(off)}$$

Plugging in your values:

$$V_{GS} \le -1.17V \rightarrow fulfilled$$

$$-7.35 > -7.4V + 1.17V=-6.23V \rightarrow unfufilled$$

NOTE: \$V_{GS(off)}=-1.17V\$ comes from the model implementation. Right click on it and you can see its properties. All the other values comes from your first simulation.

EDIT #1

Although not the most elegant solution, if you still want to use a NJFET, you have to ensure that the drain voltage of the FET is not fixed by the \$V_{FWD}\$ of the BJT. I just added some random values, and you would have to optimize it:

EDIT #2

Here is a circuit similar to the one, shown in the video. (After watching the end of the video, I almost sure that he is using a MOSFET instead of a JFET)

How it works

As you already explained, the components \$R_G\$, \$M_1\$, \$Q1\$ and \$R_b\$ form a controlled current sink. Disregarding the upper section for the moment, once the circuit is turned on, the source voltage of the MOSFET \$M_1\$ increases until it reaches \$\approx 650mV\$, thus turning on the BJT \$Q_1\$, which provides a negative feedback, which in turn reduces the \$V_{GS}\$ of the \$M_1\$.

There are two requiremts which must be fulfilled for the current source.

$$R_b > \frac{650mV}{I_{sink}}$$

AND

$$R_b > \frac{R_t\cdot 650mV}{V_{cc}-V_Z-650mV}$$

First condition ensures that there's enough current through \$R_b\$ to turn on \$Q_1\$, whereas the second one ensures that the voltage across \$R_b\$ is large enough to turn on \$Q_1\$.

The upper section of the circuit works as follows:

During start up the zener \$D_1\$ ensures that the gate voltage of \$M_2\$ is \$\approx - V_Z = -4.7V\$. At this moment the mosfet is on, and its source voltage starts to ramp ump until its \$V_{GS} < V_{th}\$ which yields an output voltage \$V_{out}\approx -15V + 4.7V + V_{th} = -7V \$