Timeline for How to determine the right microcontroller for your project?
Current License: CC BY-SA 4.0
11 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 12, 2020 at 19:11 | vote | accept | Leoc | ||
| Apr 12, 2020 at 16:07 | comment | added | Leoc | Correct, sorry for not looking more carefully. Thank you @filo | |
| Apr 12, 2020 at 16:06 | comment | added | filo | Maybe under "Instruction set summary" of the datasheet? | |
| Apr 12, 2020 at 16:05 | comment | added | Leoc | So when it says " All single-cycle instructions except for program branches, which are two-cycle" can I assume 1 cycle per operation and how would one find its instructions(POP, LOAD, ETC)? This is for the PIC16F877A as mentioned above | |
| Apr 12, 2020 at 16:00 | comment | added | filo | RISC is not about instruction execution time. You assume nothing. You read the timings out from the documentation of a particular chip. | |
| Apr 12, 2020 at 15:58 | comment | added | Leoc | Oh you're amazing thank you. Isn't all RISC CPU one clock cycle instructions though? So if I know what architecture the cpu is I can assume from there? | |
| Apr 12, 2020 at 15:51 | comment | added | filo | Regarding the PIC instruction time - you find it on the first page of the datasheet under "High-Performance RISC CPU". It is an even worse choice for DSP by the way. | |
| Apr 12, 2020 at 15:47 | comment | added | Leoc | That's a nice documented product. What if I wanted to use the PIC16F877A. How do I find its clock cycle per operations? Back to your document. I took a look at it and it measures it based on assembly? So what's executed? is it the load? or do you take it in as a whole? | |
| Apr 12, 2020 at 15:45 | comment | added | filo | Instruction lengths are documented here: infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/… in approach 2 you benchmark the just algorithm, you could though read the cycle counter at the beginning and end of the ISR to get the final timings. You will have to add some cycles for the ISR entry and exit: community.arm.com/developer/ip-products/processors/b/… | |
| Apr 12, 2020 at 15:36 | comment | added | Leoc | Thank you for an answer. In approach 1, how did you find out the Cortex-M4F can take a single clock cycle? Is this including arithmetic, variable storage etc? Approach 2: If they are both clocked, would that be a race condition as ADC needs to feed the timer in this case? and then it would need to execute it faster than it interrupts no? | |
| Apr 12, 2020 at 9:19 | history | answered | filo | CC BY-SA 4.0 |