Timeline for Single Channel ADC with DMA giving garbage results on STM32F7
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 16, 2020 at 13:02 | comment | added | user16324 | Packing 12 bits into 32 gets ugly. Padding to 16 bits is far more rational and allows compatibility between different ADCs. It's most probably a function of the ADC peripheral rather than the ADC : read the device datasheet for full details. | |
| Apr 16, 2020 at 12:55 | comment | added | Carl Gilbert | I don't follow. Why would a presumably 12-bit ADC result in values larger than 12-bit just because the data is stored in a 32-bit array? Is that a function of the DMA? | |
| Apr 16, 2020 at 11:08 | vote | accept | ChrisD91 | ||
| Apr 16, 2020 at 11:08 | comment | added | ChrisD91 | riiiiight, and this explains why exactly the second half of the buffer is empty too. I mistakenly thought that the ADC used a 32 bit data register and it does - just not for a regular single channel mode that I'm using. Only half is used and the other half is reserved. Thanks | |
| Apr 16, 2020 at 10:43 | history | answered | user16324 | CC BY-SA 4.0 |