Timeline for My VHDL doesn't detect all transitions of a signal
Current License: CC BY-SA 4.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| May 17, 2020 at 9:10 | vote | accept | ris8_allo_zen0 | ||
| May 17, 2020 at 0:18 | comment | added | D.A.S. | Beware of line inductance on 50MHz clock and radiated noise. Attempt to dampen it with say 100 ~220 Ohm terminator and see if any effects. | |
| May 16, 2020 at 21:16 | answer | added | DKNguyen | timeline score: 2 | |
| May 16, 2020 at 21:13 | history | asked | ris8_allo_zen0 | CC BY-SA 4.0 |