Timeline for Using CMOS logic ICs to drive a P-channel FET
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| May 26, 2020 at 4:09 | history | edited | Big6 | CC BY-SA 4.0 |
added 382 characters in body
|
| May 26, 2020 at 3:55 | vote | accept | Big Owls | ||
| May 25, 2020 at 23:47 | comment | added | Big6 | @user8585939 Are you sure the NMOS is oriented correctly? If you have drain and source the wrong way, the load will always be ON. On my phone will add a circuit later. | |
| May 25, 2020 at 23:32 | comment | added | Big Owls | Agree on the NAND based. Maybe I will consider the D, but one thing I liked about the SR is that it didn't force anything. In the event of the SR allowing contradictory states, that was always a wildcard, but the no change / latch aspect of it until the Reset was certainly switched high was a benefit compared to the D's forced mutual exclusion (as far as I can tell.) I can't really seem to get the circuit to work with the nFET incorporated. I guess you don't have a schematic? I have Q of the (now) 4043 hitting both gate and drain per your suggesstion, but still seems to end up always ON. | |
| May 25, 2020 at 23:08 | comment | added | Big6 | @user8585939 You can make the circuit simpler by just using a D latch. You will just have one input, D, and an Enable pin, E. The Q output will follow the input D, so long as E is asserted. You can decide what level at the D, will operate the driving FET. If you have a high level on D, Q will be high so an NMOS can be used as a low side switch to power the load. If you want the inverse logic, so that low enables the output FET, you can the use a PMOS as a high side switch. | |
| May 25, 2020 at 23:06 | comment | added | Big6 | @user8585939 Well, for a NAND based SR latch, the S=0 and R=0 is not an allow state, the same is true for a S=1, R=1 in a NOR based latch. I guess, they just give you some guarantee of what Q will be if that particular combination is asserted. | |
| May 25, 2020 at 20:55 | comment | added | Big Owls | The CD4043 has a NAND-gate equivalent which I suspect was purpose-built for this type of circumstance, which I have edited the post to include above. The only thing I don't seem to be quite clear on is why the NAND CD4044 IC would be designed such that if S=0 and R=0, it leaves Q to be dominated by the 'R=0' input. It seems like that removes a very desirable behavior of this 'latch' circuit to eliminate chatter from one end of the equation. On the 4043, it replaces this behavior with "NC," which allows the system to ride up and down undisturbed after the change in hysteresis. | |
| May 19, 2020 at 0:35 | comment | added | Big6 | @user8585939 You can do two things: Option1) Replace the PFET with an NFET, but you now need to move your load "up" and use the NFET to switch the GND instead of the +12V, as you are doing with the PFET, google NMOS low side switch. Option 2) Keep the circuit as is but use an extra transistor, an NFET. Connect the NFET's drain to the "control" node shown in my answer, the NFET's source to GND, and its gate to the 4081's output. That way your PFET will still switch the high side (+12V) to the SSR and the NFET will work as an inverter. Hope that makes sense. | |
| May 18, 2020 at 23:34 | comment | added | Big Owls | I'll consolidate my remarks for both you and Atomique's answer here, as I think they are similar in response. I do indeed have the pull-downs on S and R. They are actually 1M resistors because that's what was advised in the TI documentation for the product. Sorry for omitting that. Regarding these suggestions, thank you! I understand for the most part what needs to be done, but I am still hung up on the 4081's output. I intended / expected that to be +12V when activating SSR. Can this be done, or does it need to be inverted? Does that mean additional components or a different (NAND?) IC? | |
| May 18, 2020 at 20:12 | history | answered | Big6 | CC BY-SA 4.0 |