Timeline for How do registers connect to CPU buses
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
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| Dec 31, 2012 at 19:29 | comment | added | supercat | ...it's not difficult to design a CMOS NAND gate in such a way that if one input is low, it won't matter if the other input is mid-rail; likewise one can design a NOR gate so that if one input is high, the other won't matter. | |
| Dec 31, 2012 at 19:28 | comment | added | supercat | @DaveC: The expected design would be that every register ignores the bus except when it needs to either put its contents there or load its contents from there. Depending upon the design topology, the bus may be floating, weakly pulled high or low, weakly held in its current state (whatever that happens to be), or actively pulled high or low when nothing else is driving it. In general, CMOS gates draw extra current when their inputs are near mid-rail (and a bus which isn't driven at all could float to a near-mid-rail voltage), but... | |
| Dec 29, 2012 at 0:35 | comment | added | Trygve Laugstøl | @DaveC - Try looking at the schematics/designs of the custom/home built TTL computers out there, there's lots of nice info there. | |
| Dec 11, 2012 at 21:22 | vote | accept | Dave C | ||
| Dec 3, 2012 at 20:01 | comment | added | Dave C | Good answer; however, I'm looking more for specifics on how a 'three state ouput' would work. Do they only clock the registers that need to use the value on the databus(so the others don't change)? What type of chips between the bus/register are used? Your second paragraph has some great information, thanks! | |
| Dec 3, 2012 at 18:34 | history | answered | supercat | CC BY-SA 3.0 |