Timeline for VHDL error during synthesis, declaration and syntax error
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
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| Jan 11, 2022 at 17:16 | comment | added | user16145658 | Note component counter is never instantiated. The value assigned to phase_coh is at least 64 bits (the multiply expression needs work as well), signal phase_coh isn't evaluated and isn't needed, meaning o_count isn't needed either. i_start_phase is not evaluated either. (Looks like a missing output). | |
| Jan 11, 2022 at 16:47 | comment | added | user16145658 |
You mention one semantic error while ignoring all the syntax errors and jump to synthesis problems not yet addressed. This VHDL code isn't valid. It's missing a library clause, There are concurrent statements mixed in with declarations, constant count_no : integer := (2**32)-1; isn't portable, 2**32 is out of range of type integer for it's guaranteed range (used universally by synthesis tools). Use constant count_no: integer := integer'high; instead. isl_clk, isl_rstb, and oslv14_sine are not declared. The use of function init_lut_sin to specify the value of constant C_LUT_SIN is valid.
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| Jul 9, 2020 at 19:25 | history | edited | Vance | CC BY-SA 4.0 |
Corrected signal name
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| Jul 1, 2020 at 11:23 | history | edited | Vance | CC BY-SA 4.0 |
added 262 characters in body
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| Jul 1, 2020 at 10:21 | history | answered | Vance | CC BY-SA 4.0 |