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Timeline for Oscillating value of reset pin

Current License: CC BY-SA 4.0

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Jul 9, 2020 at 8:02 comment added Tagli As @Justme mentioned, nRST is bi-directional and goes low in case of a reset event. Maybe STM32 resets itself periodically for some reason, like WDT? Relatively steep fall seen on the graph suggests that capacitor is drained by the open-drain output of nRST pin.
Jul 8, 2020 at 15:23 comment added Justme It is. But on STMs, the capacitor keeps the voltage quite stable, and mentions of adding external pull-up has been removed years ago. The nRST pin is also bi-directional, so the resistance, if added, must be high enough not to overload the open-drain output. Any external resistance also makes the capacitor charge faster, so reset is shorter. It could be compensated by increasing the capacitance, but again, since it is bi-directional, the open-drain output is specified to discharge 100nF fast enough. The reset connection should be fine, it is made according to datasheet and eval board.
Jul 8, 2020 at 13:49 comment added Lundin It's common practice to use external, relatively low ohm pull-ups on /reset, for applications with tough EMC requirements. Since the internal one will have a very high value, though perhaps not as high as 100k.
Jul 8, 2020 at 13:14 comment added jellybean I have edited the post with the recommended suggestions but no change to it
Jul 8, 2020 at 11:47 comment added Justme The pull-up resistance is a simple resistor, nothing more. The datasheet says it right above the figure 28, that the pull-up resistance is a true resistance. Furhter above that, on previous page, it also says the nRST pin pull-up is permanently connected.
Jul 8, 2020 at 11:00 history edited JRE CC BY-SA 4.0
deleted 11 characters in body
Jul 8, 2020 at 10:36 comment added jellybean I'll check out this solution and see if it works! I know that it is not needed but I placed it there because I followed the schematic of the evaluation kit P-NUCLEO WB55
Jul 8, 2020 at 10:26 history answered miksolo CC BY-SA 4.0