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Jun 16 at 15:21 comment added flodis There seems to be some misunderstanding of the digital nature of the signal. The signal is PWM and is always either 1 or 0 . Before the inductor at 200V DC input is either 200V or 0V. It is the percentage of 1 or 0 that makes the DC signal after the inductor and output filter. The feedback signal form the voltage divider is not needed as the output is a reflection of the DC input just chopped up as defined by the digital signals already known. The only difference to the output is the resistive DC voltage component in the coil due to some DC current output if any.
Aug 31, 2020 at 1:56 answer added FrankTheTank360 timeline score: 1
Aug 21, 2020 at 19:47 comment added Cristobol Polychronopolis The diode clamp keeps the gate of the N-channel from going more than a drop below V_BOOST when the drive goes low, charging the cap to about V_BOOST. It then can rise to 5V above that level when the drive goes high. The anode should be connected to V_BOOST and the cathode to the gate.
Aug 19, 2020 at 17:10 comment added FrankTheTank360 Ok cool! Just to be super clear (sorry I'm a worrier), say Vcc is driven by 15V. Wouldn't the bootstrap diode always be reverse biased when Vout is greater than 14.3V? For example, when Vout is a sine wave, I'd only be below 14.3V for a very very short period of time.
Aug 19, 2020 at 16:44 comment added Andy aka Then use a high-side MOSFET driver is my advice. It will work fine. The bootstrapping works with the peak to peak output voltage level to generate a voltage that is about 12 volts higher than the source voltage on the top MOSFET.
Aug 19, 2020 at 16:41 comment added FrankTheTank360 @Andyaka Thanks for getting back to me Andy. So the high voltage DC rail V_boost is programmable from 50V to 250V. Let's assume I run it at 200V in this example. I would like Vout's amplitude to range from 0V to 190V, by pulsing Q_high to charge Vout up, and Q_low to discharge. Vout could take the form of a square, sine, triangle etc. wave all running at a programmable frequency (100 Hz currently).
Aug 19, 2020 at 16:37 history edited FrankTheTank360 CC BY-SA 4.0
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Aug 19, 2020 at 16:19 comment added FrankTheTank360 @CristobolPolychronopolis Thank you! I'm not really understanding how diode-clamping to V_boost would help me...I was thinking of diode clamping the gate to Vout so Vgs could always be kept below the Vgs_max of 20V. If Vg is at V_boost then Vgs_max will definitely be violated
Aug 19, 2020 at 16:16 comment added Andy aka Well you need to state values for the expected output voltage levels you desire.
Aug 19, 2020 at 16:10 comment added FrankTheTank360 @Andyaka So I agree a gate driver is likely the way to go. Referring to the typical connection diagram in the IRS20752 datasheet I don't see how the boostrap circuit would be able to generate enough voltage to charge up Q_high's gate and generate a large enough Vgs, given that Vout rarely is at ground potential (aka when the capacitor would charge up). In all the application notes I've read, the low-side MOSFET in the half-bridge drives VS to ground, and charges the boostrap capacitor, so the high-side transistor can be driven during the next on period.
Aug 18, 2020 at 19:31 history edited SamGibson CC BY-SA 4.0
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Aug 18, 2020 at 18:16 comment added Cristobol Polychronopolis You could diode-clamp the gate to V_BOOST and drive it through a capacitor, if the Vgs parameter isn't exceeded. Then your 0 to 5V signal is V_BOOST-0.7 to V_BOOST+4.3.
Aug 18, 2020 at 17:47 comment added Andy aka Well despite your worries, the answer is still a high side driver.
Aug 18, 2020 at 17:36 review First posts
Aug 22, 2020 at 15:00
Aug 18, 2020 at 17:32 history asked FrankTheTank360 CC BY-SA 4.0