Timeline for VHDL Clock Question
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 14, 2020 at 0:38 | comment | added | user8352 | rising_edge and falling_edge. Because they require a change from an effective '0' and effective '1' behavioral simulation will match synthesis models. | |
| Oct 13, 2020 at 19:57 | comment | added | user4434 | Okay, because many texts still use the if (clk'event and clk='1') then variation. Which is better for synthesis ? | |
| Oct 13, 2020 at 19:21 | comment | added | chthon | @sheeple: Yes, that was the recommendation of my teacher when I learned VHDL 10 years ago. There still seems to be old VHDL code and ways of working on the internet. | |
| Oct 13, 2020 at 18:41 | comment | added | user4434 | So would it be correct to say it might be better to use rising edge to catch all possible cases if you are using U W X Z states ? | |
| Oct 13, 2020 at 18:20 | history | answered | Dave Tweed | CC BY-SA 4.0 |