Timeline for how to design a circuit that gives high output between input transition and next rising edge of CLK
Current License: CC BY-SA 4.0
14 events
| when toggle format | what | by | license | comment | |
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| Nov 29, 2020 at 12:35 | comment | added | Firas Abd El Gani | @Andyaka Yes, I just picked the best answer. Thanks for reminding me. | |
| Nov 29, 2020 at 12:34 | vote | accept | Firas Abd El Gani | ||
| Oct 29, 2020 at 17:32 | answer | added | Jeremy Willden | timeline score: 2 | |
| Oct 28, 2020 at 23:33 | history | became hot network question | |||
| Oct 28, 2020 at 20:06 | comment | added | Elliot Alderson | You can certainly do this with a flip-flop and a logic gate, but this smells to much like homework. Why don't you tell us about the bigger picture? | |
| Oct 28, 2020 at 16:27 | history | edited | Firas Abd El Gani | CC BY-SA 4.0 |
added 281 characters in body
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| Oct 28, 2020 at 16:02 | history | edited | jsotola | CC BY-SA 4.0 |
clarified title
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| Oct 28, 2020 at 15:49 | comment | added | Finbarr | Why do you need to do this? There are pitfalls, particularly with the setup time to the clock edge. You might miss the rising edge of IN altogether. Or you may end up with an OUT pulse too small for whatever it's going into to recognise it. | |
| Oct 28, 2020 at 15:47 | answer | added | Andy aka | timeline score: 4 | |
| Oct 28, 2020 at 15:47 | answer | added | Aaron | timeline score: 3 | |
| Oct 28, 2020 at 15:45 | comment | added | Firas Abd El Gani | I modified the diagram. thanks for the note. | |
| Oct 28, 2020 at 15:41 | history | edited | Firas Abd El Gani | CC BY-SA 4.0 |
deleted 2 characters in body
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| Oct 28, 2020 at 15:30 | comment | added | Eugene Sh. | The diagram is not clear enough. When the first transition is happening? When the rising transition of the second output plus is happening? | |
| Oct 28, 2020 at 15:27 | history | asked | Firas Abd El Gani | CC BY-SA 4.0 |