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Timeline for XILINX Vivado VHDL using "printf"

Current License: CC BY-SA 4.0

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Nov 30, 2020 at 19:28 comment added Chris Stratton Indeed. The other choice is to give the design itself some sort of output, but that's typically more sensible when it's a functional rather than purely debug goal.
Nov 30, 2020 at 19:15 history answered Peter Green CC BY-SA 4.0