Timeline for Choice of P or N channel device as active load
Current License: CC BY-SA 4.0
11 events
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| Dec 7, 2020 at 5:27 | comment | added | nanofarad | @anrieff I thought about your topology a little more deeply and I don't think it will work as well as expected -- even though the Vgs of the two FETs is different, they have the same topological issue where the Vgs is taken relative to the output (since that's where the source is). As far as I can see, all that we get is a degenerated version of the undesired feedback structure, and we're doing no better than just a resistor, or a PMOS active load. | |
| Dec 4, 2020 at 17:59 | comment | added | nanofarad | @ModularMan Negative feedback is indeed one way to look at the structure that is created -- the nice (or maybe scary) thing is that these topologies can be unfolded and analyzed in a number of different ways. I could also look at this as a poorly made common-drain buffer that buffers the constant bias voltage applied to its input (top gate), while its NMOS active load (bottom FET) has a fluctuating gate voltage. Such an interpretation isn't necessarily the one that comes naturally, but it isn't too far of a stretch. | |
| Dec 4, 2020 at 17:57 | comment | added | ModularMan | This is a great explanation and exactly what I was looking for, thank you, nanofarad. So the main reasoning is that by using an NMOS as an active load for an NMOS CS amp, we are creating negative feedback by varying the Vgs of the active load NMOS, thus not creating a constant current source? | |
| Dec 4, 2020 at 4:41 | comment | added | nanofarad | @anrieff I suspect that this arrangement gives poor output impedance because of the source voltage varying with the drain current of the bottom FET -- I'd need to think about it more closely with either math or simulation to fully understand it. | |
| Dec 4, 2020 at 4:15 | comment | added | anrieff | In discrete design you'd need to add a resistor downstream of the top FET, and tie its gate to the node after the resistor (which is also the Vout node). Then the Vgs of the two FETs will be different, and of course their effective Vth is different. I think it might work. | |
| Dec 4, 2020 at 3:58 | history | edited | nanofarad | CC BY-SA 4.0 |
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| Dec 4, 2020 at 3:57 | comment | added | nanofarad | @anrieff The process I used did not provide depletion-mode FETs, so I'm not familiar with their behavior. I would suspect that it still wouldn't work because the channel still has the same source/drain, just that the band structure in the channel makes for an effectively negative threshold voltage without changing the differential/small-signal behavior. | |
| Dec 4, 2020 at 3:54 | comment | added | anrieff | If the top FET is a depletion-mode nFET, configured as a current source, wouldn't the amplifier work? I believe nobody is using depletion-mode FETs in IC design nowadays, so the PMOS solution is preferred. | |
| Dec 4, 2020 at 3:41 | vote | accept | ModularMan | ||
| Dec 4, 2020 at 3:17 | history | edited | nanofarad | CC BY-SA 4.0 |
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| Dec 4, 2020 at 3:11 | history | answered | nanofarad | CC BY-SA 4.0 |