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Dec 10, 2020 at 19:24 comment added user136077 Listen, buddy! These models are idealized. They assume all capacitances=zero inside the fet. Zero capacitance between 2 points means no connection between those points caused by capacitors. These models are different simple circuits which all satisfy equations Id=(Vgs)*(gm). AND Ig=0. These models do not claim to present the structure of a real fet except the fact that there are three wires named D,G and S.
Dec 10, 2020 at 13:39 comment added Mahmoud Salah the 1/gm resistance is in series with the drain resistance and gate is just very high resistance how is it possible to say that it's just 1/gm ?? it can't be 1/gm unless we assume the gate is short circuit in the analysis but appearently we didn't...
Dec 10, 2020 at 13:37 comment added Mahmoud Salah Yes but it's a capacitive gate so Shouldn't it be a short in the analysis? if not How the resistance is very small when looking from the source if there will be no path (ideally) between the gate and the source as assumed in the first case it just doesn't make sense to me
Dec 10, 2020 at 12:28 comment added user136077 Can you possibly see how two 10 Ohm resistors in parallel with no other parts produce total 5 Ohm resistance? There's also 2 different values, no matter there's only 10 Ohm resistors. The equivalent resistance 5 Ohm can be calculated with circuit analysis. A calculation of the equivalent resistance between G and S will produce infinite (=zero total conductance).
Dec 10, 2020 at 12:25 comment added Mahmoud Salah It doesn't matter if the Resistor value is too high or infinite it's just confusing to me that there's a very high resistance value in one configuration and very small one in the other clearly no matter what the gate current will be very small
Dec 10, 2020 at 12:21 comment added Mahmoud Salah I don't get how this explain the two different resistance values in both cases
Dec 10, 2020 at 12:20 history edited user136077 CC BY-SA 4.0
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Dec 10, 2020 at 12:10 history answered user136077 CC BY-SA 4.0