There is no difference in the two examples you wrote. You can even make is simpler:

module counter (
  input  wire clk, clr,
  output reg [3:0] q
);
always @(posedge clk or posedge clr)
begin
   if (clr)
      q<= 4’b0000;
   else
      q<= q+ 1’b1;
end

endmodule

There is no difference in the two examples you wrote. You can even make is simpler:

module counter (
  input  wire clk, clr,
  output reg [3:0] q
);
always @(posedge clk or posedge clr)
begin
   if (clr)
      q<= 4'b0000;
   else
      q<= q+ 1'b1;
end

endmodule