Timeline for Memory To Memory DMA on STM32
Current License: CC BY-SA 4.0
3 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jan 19, 2021 at 19:33 | comment | added | DKNguyen | @Amin Wiggle the correct registers. It will involve writing the source address and destination address, how much data to transfer and probably how wide the datawidth is, and a few control bits to initiate. Read the user reference manual | |
| Jan 19, 2021 at 19:31 | comment | added | Justme | As explained by the reference manual, and DMA application notes, the enable bit (EN) triggers the transfer. | |
| Jan 19, 2021 at 18:59 | history | answered | Justme | CC BY-SA 4.0 |