Timeline for Altera Quartus detects 2 CPLD devices instead of 1
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 26, 2021 at 15:48 | vote | accept | user3161354 | ||
| Feb 26, 2021 at 15:46 | answer | added | Tom Carpenter | timeline score: 2 | |
| Feb 26, 2021 at 15:46 | answer | added | user3161354 | timeline score: 1 | |
| Feb 26, 2021 at 15:40 | comment | added | Tom Carpenter | Furthermore, your VccTRGT for the JTAG header should be to 3.3V as all of your VCCIO pins are driven at 3.3V | |
| Feb 26, 2021 at 15:40 | comment | added | Tom Carpenter | Per this, the TCK needs a 1k pull down. TMS and TDI need 10k pull ups to VCCIO1. | |
| Feb 26, 2021 at 15:10 | comment | added | user3161354 | Uploaded the schematic now | |
| Feb 26, 2021 at 15:09 | history | edited | user3161354 | CC BY-SA 4.0 |
added 201 characters in body
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| Feb 26, 2021 at 14:25 | comment | added | Tom Carpenter | There is an issue with your board or programmer. Possibly a short, possibly you're using the wrong voltage, possibly you've missed a pull-up resistor on some configuration pin somewhere. However as you haven't shared any photos or diagrams of your circuit and schematic, there is little we can do to help | |
| Feb 26, 2021 at 14:02 | history | asked | user3161354 | CC BY-SA 4.0 |