Timeline for 7408 quad-AND with diode latching: sporadic (and undesired) self-latching at power up
Current License: CC BY-SA 4.0
11 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 14, 2021 at 18:16 | vote | accept | Ad N | ||
| Mar 13, 2021 at 12:54 | comment | added | Elliot Alderson | @vangelo Manufacturers don't put such information in every datasheet because it would be a waste of paper (electrons? photons?). Usually they will publish one document that describes how a particular logic family is designed and constructed, and that document applies to all devices in that logic family. | |
| Mar 13, 2021 at 12:16 | comment | added | jwh20 | @vangelo If the manufacturer doesn't publish that information, your guess is as good as mine. But the general design of a CMOS AND gate is well established. Here is a reference that describes the basic design: computationstructures.org/notes/cmos/notes.html | |
| Mar 13, 2021 at 12:12 | comment | added | devnull | @jwh20 Could you please share with us an internal schematic showing how this specific and gate is implemented? I've tried 4 different manufacturers datasheets and the "best" I could find was one which gives an "Input and output equivalent circuit", overly simplified, just with diodes and a CMOS pair. | |
| Mar 13, 2021 at 11:59 | comment | added | jwh20 | The pulldown doesn't guarantee that the input will be 0 at power-up since the output of the AND gate may be a 1 and will force the input to a 1 through the diode. The capacitor adds delay so that even if the output is 1, it will not have enough time to charge the capacitor so that the input is also a 1. Circuits like this can be very problematic in the real world and should be avoided if possible. | |
| Mar 13, 2021 at 11:54 | history | edited | jwh20 | CC BY-SA 4.0 |
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| Mar 13, 2021 at 11:53 | comment | added | Ad N | @vangelo I was editing and testing my circuit, and it seems to be an efficient solution indeed! Now I have to understand why the capacitor ensures 0V more efficiently than a pull-down resistor directly connecting to the 0V rail. | |
| Mar 13, 2021 at 11:46 | comment | added | devnull | @AdN, Have you tried Finbarr's suggestion above? (e. g. 10nF) | |
| Mar 13, 2021 at 11:45 | history | edited | jwh20 | CC BY-SA 4.0 |
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| Mar 13, 2021 at 11:28 | comment | added | Ad N | Thank you for your explanation. Can you provide designs or pointers for an appropriate power-on-reset circuit? | |
| Mar 13, 2021 at 11:24 | history | answered | jwh20 | CC BY-SA 4.0 |