Present (series 7) Xilinx FPGAs support a number of methods to load the bitstream:
- Master-Serial configuration mode
- Slave-Serial configuration mode
- Master SelectMAP (parallel) configuration mode (x8 and x16)
- Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)
- JTAG/boundary-scan configuration mode
- Master Serial Peripheral Interface (SPI) flash configuration mode (x1, x2, x4)
- Master Byte Peripheral Interface (BPI) flash configuration mode (x8 and x16) using parallel NOR flash
From here: https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
All of the 'slave' modes can be implemented by a microcontroller, with the Slave-Serial requiring the fewest pins.
Large Virtex devices (Ultrascale) support a 'Tandem' mode which allows a small bitstream to be loaded first (e.g., from SPI), then the rest over a fast interface like PCIe.
It is also possible to use the Master SPI mode, then offer the capability to re-flash in system remotely by instancing a SPI interface in the design, that can take over the Flash SPI pins once configuration is done. More here: https://forums.xilinx.com/t5/FPGA-Configuration/SPI-Flash-reconfiguration-a-modest-proposal/td-p/947747
Now, what does Microsemi support? For Polarfire, a subset of what Xilinx supports, namely:
- JTAG
- Master SPI (with a multi-image use model, like SelectMap)
- Slave SPI
So seems like you could support the Slave SPI mode for in-system reconfiguration, as well as JTAG for debug.
From this list: https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/56758-soc/56827-silicon-user-s-guides