Timeline for Is it possible to use an if then clause within a for generate clause in VHDL?
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
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| Jun 5, 2021 at 20:49 | vote | accept | goahead97 | ||
| Jun 5, 2021 at 17:17 | comment | added | user16324 |
if ... then must be used inside a process (which can be inside a generate). But you probably meant if ... generate
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| Jun 5, 2021 at 11:39 | answer | added | Simon Richter | timeline score: 2 | |
| Jun 5, 2021 at 11:13 | comment | added | Marcus Müller | "does not compile": indicates the errors you get are potentially telling you what is wrong. | |
| Jun 5, 2021 at 11:01 | review | First posts | |||
| Jun 5, 2021 at 22:11 | |||||
| Jun 5, 2021 at 10:57 | history | asked | goahead97 | CC BY-SA 4.0 |