Timeline for Problem of metastability: simulation of dual port ram
Current License: CC BY-SA 4.0
14 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jun 21, 2021 at 16:47 | comment | added | Ben Voigt | @Neil_UK: "which go to sufficient sigma". See, you do know it happens with a (very low) probability. How many sigma do you think "ten.billion.human.second.century" is? | |
| Jun 21, 2021 at 16:38 | comment | added | Neil_UK | @BenVoigt metastability shouldn't occur in a well-designed single clock fully synchronous design, not if the timing analyser uses min and max timings which go to sufficient sigma. Are you saying the timing data is not conservative enough? Instantiate, implement, whatever. The question asked should be unasked, the correct answer is don't do it that way. | |
| Jun 21, 2021 at 15:17 | comment | added | Ben Voigt | Possibly you meant "The correct way to instantiate dual port RAM" and not "to implement", in which case I would agree with you. And it would still not be an answer to the question asked. | |
| Jun 21, 2021 at 15:15 | comment | added | Ben Voigt | Also note that metastability also occurs in a single clock fully synchronous design, with some very-low probability which in many cases is still much higher than the target you mention. | |
| Jun 21, 2021 at 15:13 | comment | added | Ben Voigt | What you describe is not actually dual-port RAM (two control ports each with its own clock), but a dual-issue RAM (two control ports sharing a clock). It may be useful for most of the same applications in practice, and easier to reason about... but it is not an answer to the question. | |
| Jun 21, 2021 at 13:20 | history | edited | Neil_UK | CC BY-SA 4.0 |
added 364 characters in body
|
| Jun 21, 2021 at 8:59 | comment | added | Neil_UK | @LeeLeeYa You don't necessarily need pipelined latches to drive the probability of metastability down, you just have to wait long enough. However, if your system clock period is less than the time you need to wait, then you must use a pipeline of latches to implement the wait. | |
| Jun 21, 2021 at 8:57 | history | edited | Neil_UK | CC BY-SA 4.0 |
added 326 characters in body
|
| Jun 21, 2021 at 7:36 | vote | accept | LeeLeeYa | ||
| Jun 21, 2021 at 7:35 | vote | accept | LeeLeeYa | ||
| Jun 21, 2021 at 7:36 | |||||
| Jun 21, 2021 at 7:11 | comment | added | Neil_UK | The clk_crossing process is using pipelined latches. So it's doing the right thing in order to minimise problems, but it's doing it in the wrong place. It's rather like commiting a murder, and then recycling the weapon in an eco-friendly way. You're doing the right eco thing, but in the commission of a heinous clk_crossing deed. Don't do the murder. Use a single clock for the RAM. Redesign for clock enables. | |
| Jun 21, 2021 at 7:07 | comment | added | LeeLeeYa | I have read about pipelined latches. The process "clk_crossing" is an implementation of it, isnt? | |
| Jun 21, 2021 at 7:05 | history | edited | Neil_UK | CC BY-SA 4.0 |
added 503 characters in body
|
| Jun 21, 2021 at 6:45 | history | answered | Neil_UK | CC BY-SA 4.0 |