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Your stackup looks good to me. but this conclusion only applies for this stackup. Other stackups with e.g. layers 3 and 4 tightly spaced will not work

But with this stackup that you posted, the crosstall between layers 3 and 4 should be absolutely minimal if at all detectable. Everything in layer 3 will be referred to layer 2 and everything in layer 4 to layer 5.

If you have a signal in 3 and a power poly in 4, consequently, it will have pretty minimal coupling and there is no problem routing over edges of the power poly, simple because the signal is fully referred to layer 2 and doesn’t "see" the power poly. Just compare the impedance of the signal if you a) have only gnd in 2 to b) when there is also copper in 4 additionally. there will be almost no difference. Think of an ant crawling on your ceiling: it doesnt care if there are holes in your floor because it is fully referred to the ceiling. The ant is layer 3, ceiling layer 2 and floor layer 4.

The second question is if signals in 4 care about the power poly in 4. Again, not a lot, if you keep the signals at least about 15 mil (3 H) away from the poly.

Therefore, I consider 3 and 4 the best layers for your power polys, because you can bring the poly right under the ICs and have minimum supply inductance.

Just make sure that when you cross anything from the top layer triplet to bottom, that you provide sufficient gnd vias nearby, so return currents can transition between layers 2 and 5. Crossing without GND vias is only ok, if you cross between 1 and 3 or between 4 and 6. However, tracewidths must be different on layers 1 and 3, but you are probably aware of that and impedance calculation when you design such a board..:-)

Your stackup looks good to me, though this conclusion only applies for this stackup. Other stackups with e.g. layers 3 and 4 tightly spaced will not work.

But with this stackup that you posted, the crosstalk between layers 3 and 4 should be absolutely minimal if at all detectable. Everything in layer 3 will be referred to layer 2 and everything in layer 4 to layer 5.

If you have a signal in 3 and a power poly in 4, consequently, it will have pretty minimal coupling and there is no problem routing over edges of the power poly, simple because the signal is fully referred to layer 2 and doesn’t "see" the power poly. Just compare the impedance of the signal if you a) have only gnd in 2 to b) when there is also copper in 4 additionally. there will be almost no difference. Think of an ant crawling on your ceiling: it doesnt care if there are holes in your floor because it is fully referred to the ceiling. The ant is layer 3, ceiling layer 2 and floor layer 4.

The second question is if signals in 4 care about the power poly in 4. Again, not a lot, if you keep the signals at least about 15 mil (3 H) away from the poly.

Therefore, I consider 3 and 4 the best layers for your power polys, because you can bring the poly right under the ICs and have minimum supply inductance.

Just make sure that when you cross anything from the top layer triplet to bottom, that you provide sufficient gnd vias nearby, so return currents can transition between layers 2 and 5. Crossing without GND vias is only ok, if you cross between 1 and 3 or between 4 and 6. However, tracewidths must be different on layers 1 and 3, but you are probably aware of that and impedance calculation when you design such a board..:-)

Your stackup looks good to me. but this conclusion only applies for this stackup. Other stackups with e.g. layers 3 and 4 tightly spaced will not work

But with this stackup that you posted, the crosstall between layers 3 and 4 should be absolutely minimal if at all detectable. Everything in layer 3 will be referred to layer 2 and everything in layer 4 to layer 5.

If you have a signal in 3 and a power poly in 4, consequently, it will have pretty minimal coupling and there is no problem routing over edges of the power poly, simple because the signal is fully referred to layer 2 and doesn’t "see" the power poly. Just compare the impedance of the signal if you a) have only gnd in 2 to b) when there is also copper in 4 additionally. there will be almost no difference. Think of an ant crawling on your ceiling: it doesnt care if there are holes in your floor because it is fully referred to the ceiling. The ant is layer 3, ceiling layer 2 and floor layer 4.

Just make sure that when you cross anything from top to bottom, that you provide sufficient gnd vias nearby, so return currents can transition between layers 2 and 5. Crossing without GND vias is only ok, if you cross between 1 and 3 or between 4 and 6. However, tracewidths must be different on layers 1 and 3, but you are probably aware of that and impedance calculation when you design such a board..:-)

Your stackup looks good to me. but this conclusion only applies for this stackup. Other stackups with e.g. layers 3 and 4 tightly spaced will not work

But with this stackup that you posted, the crosstall between layers 3 and 4 should be absolutely minimal if at all detectable. Everything in layer 3 will be referred to layer 2 and everything in layer 4 to layer 5.

If you have a signal in 3 and a power poly in 4, consequently, it will have pretty minimal coupling and there is no problem routing over edges of the power poly, simple because the signal is fully referred to layer 2 and doesn’t "see" the power poly. Just compare the impedance of the signal if you a) have only gnd in 2 to b) when there is also copper in 4 additionally. there will be almost no difference. Think of an ant crawling on your ceiling: it doesnt care if there are holes in your floor because it is fully referred to the ceiling. The ant is layer 3, ceiling layer 2 and floor layer 4.

The second question is if signals in 4 care about the power poly in 4. Again, not a lot, if you keep the signals at least about 15 mil (3 H) away from the poly.

Therefore, I consider 3 and 4 the best layers for your power polys, because you can bring the poly right under the ICs and have minimum supply inductance.

Just make sure that when you cross anything from the top layer triplet to bottom, that you provide sufficient gnd vias nearby, so return currents can transition between layers 2 and 5. Crossing without GND vias is only ok, if you cross between 1 and 3 or between 4 and 6. However, tracewidths must be different on layers 1 and 3, but you are probably aware of that and impedance calculation when you design such a board..:-)

Your stackup looks good to me. but this conclusion only applies for this stackup. Other stackups with e.g. layers 3 and 4 tightly spaced will not work

But with this stackup that you posted, the crosstall between layers 3 and 4 should be absolutely minimal if at all detectable. Everything in layer 3 will be referred to layer 2 and everything in layer 4 to layer 5.

If you have a signal in 3 and a power poly in 4, consequently, it will have pretty minimal coupling and there is no problem routing over edges of the power poly, simple because the signal is fully referred to layer 2 and doesn’t "see" the power poly. Just compare the impedance of the signal if you a) have only gnd in 2 to b) when there is also copper in 4 additionally. there will be almost no difference. Think of an ant crawling on your ceiling: it doesnt care if there are holes in your floor because it is fully referred to the ceiling.

Just make sure that when you cross anything from top to bottom, that you provide sufficient gnd vias nearby, so return currents can transition between layers 2 and 5. Crossing without GND vias is only ok, if you cross between 1 and 3 or between 4 and 6. However, tracewidths must be different on layers 1 and 3, but you are probably aware of that and impedance calculation when you design such a board..:-)

Your stackup looks good to me. but this conclusion only applies for this stackup. Other stackups with e.g. layers 3 and 4 tightly spaced will not work

But with this stackup that you posted, the crosstall between layers 3 and 4 should be absolutely minimal if at all detectable. Everything in layer 3 will be referred to layer 2 and everything in layer 4 to layer 5.

If you have a signal in 3 and a power poly in 4, consequently, it will have pretty minimal coupling and there is no problem routing over edges of the power poly, simple because the signal is fully referred to layer 2 and doesn’t "see" the power poly. Just compare the impedance of the signal if you a) have only gnd in 2 to b) when there is also copper in 4 additionally. there will be almost no difference. Think of an ant crawling on your ceiling: it doesnt care if there are holes in your floor because it is fully referred to the ceiling. The ant is layer 3, ceiling layer 2 and floor layer 4.

Just make sure that when you cross anything from top to bottom, that you provide sufficient gnd vias nearby, so return currents can transition between layers 2 and 5. Crossing without GND vias is only ok, if you cross between 1 and 3 or between 4 and 6. However, tracewidths must be different on layers 1 and 3, but you are probably aware of that and impedance calculation when you design such a board..:-)