Timeline for Gate driving loss and gate driver for Buck
Current License: CC BY-SA 4.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 21, 2021 at 20:30 | comment | added | KiDMiO | Ok thanks very much so by calculating QgVddfsw i obtain the total driving losses which should be equal to Vdd*Idd and comprehend everything from driver to driving process | |
| Aug 21, 2021 at 20:20 | comment | added | jp314 | In that document, Icc is not associated with the drivers or FETs, but the remainder of the DCDC's controller -- opamps, bias etc. | |
| Aug 21, 2021 at 19:57 | comment | added | KiDMiO | Thanks very much for the response. In my testbench i have an n-n configuration supplied by Vbatt and two drivers supplied by Vdd. Drivers are made by a chain of inverters. What i was doing is calculate Vdd*Idd and then add QgVddfsw where Q is obtained by integrating current supplied by driver over a period. Basically something similar to this fscdn.rohm.com/en/products/databook/applinote/ic/power/… where driver loss is called IC loss | |
| Aug 21, 2021 at 19:21 | history | answered | jp314 | CC BY-SA 4.0 |