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Transistor
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  • Instead of thinking of currents think of voltages.

enter image description here

Figure 1. Computer architecture showing address, data and control busses. Source: Wikispaces.

  • Remember that "bus" is short for "omnibus" (Latin) which means "for all".
  • If any device applies a voltage onto the bus then all others connected to the bus can see it and read it.

... how is the current maintained when it is being split into the the other registers' inputs?

Each logic device will have a rated output "fan-out" which tells you how many inputs can be fed from that output. This used to be a big issue with TTL logic which had high input currents but isn't generally an issue on CMOS as the input resistance is so high that negligible current is drawn (other than to charge up the input capacitance). You can generally consider the inputs as voltage driven.

It might be worth noting that each device on the bus allwill load the bus whether enabled or not because the enable/disable feature will be implemented after the input buffer (which is what creates the bus load).

See my answer to What is a bus (physically) in digital design? which has more on the topic.

  • Instead of thinking of currents think of voltages.
  • Remember that "bus" is short for "omnibus" (Latin) which means "for all".
  • If any device applies a voltage onto the bus then all others connected to the bus can see it and read it.

... how is the current maintained when it is being split into the the other registers' inputs?

Each logic device will have a rated output "fan-out" which tells you how many inputs can be fed from that output. This used to be a big issue with TTL logic which had high input currents but isn't generally an issue on CMOS as the input resistance is so high that negligible current is drawn (other than to charge up the input capacitance). You can generally consider the inputs as voltage driven.

It might be worth noting that each device on the bus all load the bus whether enabled or not because the enable/disable feature will be implemented after the input buffer (which is what creates the bus load).

  • Instead of thinking of currents think of voltages.

enter image description here

Figure 1. Computer architecture showing address, data and control busses. Source: Wikispaces.

  • Remember that "bus" is short for "omnibus" (Latin) which means "for all".
  • If any device applies a voltage onto the bus then all others connected to the bus can see it and read it.

... how is the current maintained when it is being split into the the other registers' inputs?

Each logic device will have a rated output "fan-out" which tells you how many inputs can be fed from that output. This used to be a big issue with TTL logic which had high input currents but isn't generally an issue on CMOS as the input resistance is so high that negligible current is drawn (other than to charge up the input capacitance). You can generally consider the inputs as voltage driven.

It might be worth noting that each device on the bus will load the bus whether enabled or not because the enable/disable feature will be implemented after the input buffer (which is what creates the bus load).

See my answer to What is a bus (physically) in digital design? which has more on the topic.

Source Link
Transistor
Transistor
  • 180.6k
  • 14
  • 195
  • 418

  • Instead of thinking of currents think of voltages.
  • Remember that "bus" is short for "omnibus" (Latin) which means "for all".
  • If any device applies a voltage onto the bus then all others connected to the bus can see it and read it.

... how is the current maintained when it is being split into the the other registers' inputs?

Each logic device will have a rated output "fan-out" which tells you how many inputs can be fed from that output. This used to be a big issue with TTL logic which had high input currents but isn't generally an issue on CMOS as the input resistance is so high that negligible current is drawn (other than to charge up the input capacitance). You can generally consider the inputs as voltage driven.

It might be worth noting that each device on the bus all load the bus whether enabled or not because the enable/disable feature will be implemented after the input buffer (which is what creates the bus load).