Timeline for MUX between 2 digital signals so that one is normally connected and the other is in high Z without any power draw
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
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| Dec 28, 2021 at 17:24 | comment | added | user131342 | @user733606 Beware of the temperature range when reading input leakage current. The data sheet you reference shows input leakage of ±0.1uA max at 25°C; even over the full military range of -40°C to +125°C it is only ±0.75uA | |
| Dec 27, 2021 at 15:16 | comment | added | tobalt | @user733606 Read the note [1] in the datasheet. This additional supply current in not relevant in a static scenario. It only briefly appears when there is a logic transition at the input, due to shootthrough of the logic transistors. When the inputs are all either at VDD or VSS, then the consumption is extremely small. | |
| Dec 27, 2021 at 15:09 | comment | added | user733606 | @henros I agree that it sound excessive. For example: assets.nexperia.com/documents/data-sheet/74AUP2G157.pdf | |
| Dec 27, 2021 at 10:13 | comment | added | user131342 | "Standard" CMOS static input currents are normally specified as a maximum of 0.1uA This is because of the limitations of calibrating the test equipment; as @tobait says, actual input currents are usually negligible and are difficult to distinguish from surface leakage. 100uA for an input seems ridiculously high when the static consumption for the entire IC can be a maximum of 5uA. | |
| Dec 27, 2021 at 9:11 | comment | added | user733606 | I know that in theory the current consumption should be near 0, however all devices I've managed to find are 50 to 100uA. | |
| Dec 27, 2021 at 8:36 | comment | added | tobalt | @user733606 The selection pin (when static) draws more like 1 pA. It is really just a MOSFET gate. It can be easily provided by a 1 MOhm pulldown. Such a mux gate as a whole, when static also consumes essentially no power in total (well under 1 µA). But if you have no access to a logic voltage, then it won't work indeed. | |
| Dec 27, 2021 at 8:17 | comment | added | user733606 | They requirement the selection pins to be held at specific logic levels at all times + they draw around 100uA at all times. As I wrote, I am after a solution that does not draw any power. | |
| Dec 27, 2021 at 8:13 | history | answered | tobalt | CC BY-SA 4.0 |