Timeline for FPGA counter works in simlation, not in hardware
Current License: CC BY-SA 4.0
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| Feb 24, 2022 at 12:57 | comment | added | physguy | Thanks! I actually use only the button as a "clock", so there is no other (system) clock (as far as I know). I was also suspecting a timing issue, but curiously, it is the first flop (bit 0) that acts up, which has no other signal going to it other than my button. I'll try the "synchronizer" tip tonight! | |
| Feb 23, 2022 at 8:11 | comment | added | Vladimir Cravero | To be fair, he does have two "clocks": the system clock and the button clock. I am surprised that without synchronization the pattern is repeatable - I would expect setup/hold times to fail randomly as the button edge is asynchronous. | |
| Feb 23, 2022 at 8:04 | history | answered | Miron | CC BY-SA 4.0 |