Timeline for Verilog "bus switching"
Current License: CC BY-SA 4.0
3 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 27, 2022 at 5:27 | comment | added | SparkyNZ | I'm going to accept your answer @Dave Tweed. After experimenting with continuous assignments and functions, I'm definitely going to create a module. I just need an input and an output port for each bus/signal that needs to be switched. Thank you! | |
| Mar 27, 2022 at 5:25 | vote | accept | SparkyNZ | ||
| Mar 26, 2022 at 16:25 | history | answered | Dave Tweed | CC BY-SA 4.0 |