Timeline for Mapping different resolution ADC to DAC
Current License: CC BY-SA 4.0
3 events
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| Apr 20, 2022 at 11:46 | comment | added | Neil_UK | Yes, your numbers are correct. However, we never divide in hardware if we can help it, always multiply, so by 1/7.2 = 0.1389. However, that's very close to 0.125 (1/8) which we can get with a 3 bit right shift, which costs exactly zero in FPGA resources, if the approximation is good enough for you. If not, then expand 0.1389 as a binary fraction, and add as many terms as you need, at the cost of n-1 adders for n bits. For instance with only two terms, binary fraction 0.001001 = 0.1406 | |
| Apr 20, 2022 at 10:12 | comment | added | Shannon | Got it, my DAC FS is 18V while ADC FS is 2.5V thus the FPGA has to divide the value by ~7.2 to map ADC FS to DAC correct? if so, is this division feasible with FPGA or it will take a lot of resources? | |
| Apr 20, 2022 at 8:06 | history | answered | Neil_UK | CC BY-SA 4.0 |