Timeline for LTspice, modeling line driver with propagation delay (LH0063)
Current License: CC BY-SA 4.0
15 events
| when toggle format | what | by | license | comment | |
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| Sep 23, 2022 at 13:50 | vote | accept | Tony | ||
| Sep 20, 2022 at 10:21 | answer | added | Antonio51 | timeline score: 0 | |
| Sep 19, 2022 at 21:18 | comment | added | Tony | I was trying to get something working using the level.3b opamp... No success, I'm going with the BV source with tripdv/tripdt solution. | |
| Sep 16, 2022 at 18:03 | comment | added | Ste Kulov |
SPICE has an internal timestep control algorithm to determine when it should calculate data or not. Setting the max parameter in .tran forces it to never go beyond that step size but it can go below if the algorithm decides to. Downside is that it'll waste time calculating timesteps when nothing is changing and things are idle. If you set the tripdv/tripdt parameters in the BV source you can avoid that inefficiency. I can make all this an official answer if you think it's worth it.
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| Sep 16, 2022 at 14:35 | comment | added | Tony | BV(delay) does work in AC!... I heard otherwise and believed it. Reducing the step size fixes the problem! I saw the suggestion but assumed it was not the problem because other hard edges were being simulated correctly... I'm still working on this, should have a concise solution by the end of the day. | |
| Sep 16, 2022 at 7:51 | comment | added | Ste Kulov | Screenshot of what I'm talking about. Adding the tripdv/tripdt to the B-source also fixes the slew (i.e. the timestep error) on the tline path. V(out) and V(out2) are right on top of each other. Also, here's a reference for those parameters. | |
| Sep 16, 2022 at 7:48 | comment | added | Ste Kulov |
You gave no feedback on my suggestion of universally reducing the maximum timestep, so I'll assume you don't like it because it slows the simulation down and the user of your subcircuit needs to know to reduce it. One way around that is by forcing a timestep reduction based on the signal slew. You can use tripdv and tripdt parameters of a B-source to do this. You can actually still use the tline for your signal path (if you prefer; you still haven't explained why) and throw the B-source off to the side, since its sole purpose would be to force the timesteps for the rest of the circuit.
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| Sep 15, 2022 at 21:23 | comment | added | Tony | I spent the afternoon messing with level.3b... Hard to figure the right combination of GBW, phase margin and slew that produce the right results. The 'delay' is a function a of all 3 of theses. | |
| Sep 15, 2022 at 19:17 | comment | added | Ste Kulov |
@Andyaka It does not, explicitly. But I looked at the subcircuit for DELAY.MAC in MicroCap and it uses a transmission line too but adds VCVS (E-source) buffers at the input and output to isolate the tline's other, likely unwanted, effects.
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| Sep 15, 2022 at 18:54 | comment | added | a concerned citizen |
Use level.3b with appropriate settings and you should get a built-in analog delay, which may be better than the tline due to the continuous nature of the tie response. Here's a quick test.
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| Sep 15, 2022 at 18:45 | comment | added | Ste Kulov | @Tony #fakenews. Can you show an example of it not working? Or clarify what specifically doesn't work? Because I can show the opposite. My group delays match. i.sstatic.net/ihrRZ.png | |
| Sep 15, 2022 at 18:34 | comment | added | Tony | The BV source with the delay() function does NOT work for AC analysis. | |
| Sep 15, 2022 at 18:31 | comment | added | Ste Kulov |
Set your maximum timestep in the .tran statement to something like 1p. You can also try the delay or absdelay functions with a B-source, but I think you'll have the same problem. See the "B. Arbitrary Behavioral Voltage or Current Sources" section of the LTspice help for syntax of those functions.
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| Sep 15, 2022 at 18:02 | comment | added | Andy aka | Doesn't LTSpice have a thing called an analogue delay macro (as per micro-cap)? | |
| Sep 15, 2022 at 17:54 | history | asked | Tony | CC BY-SA 4.0 |
