Timeline for Verilog gate-level modelling of the JK flip-flop
Current License: CC BY-SA 4.0
4 events
| when toggle format | what | by | license | comment | |
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| Oct 24, 2022 at 16:28 | history | edited | blackblade | CC BY-SA 4.0 |
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| Oct 24, 2022 at 16:18 | comment | added | blackblade | Wait, if q is 0 then qbar should be 1 and vice versa. Can you try again? | |
| Oct 24, 2022 at 14:16 | comment | added | verilog_newb | Thanks! I was able to force q and qbar to 0 at the initiate begin. their status doesn't change in the 400 ns I simulated. Is it because I have to simulate the wires (nand1_out and nand2_out) in the original source code as well? How do I classify them? I tried both reg and wire, each fails the sim.. | |
| Oct 24, 2022 at 13:26 | history | answered | blackblade | CC BY-SA 4.0 |