Timeline for 3.3 V level P-channel MOSFET diagram
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 22, 2022 at 0:16 | vote | accept | Vera Fodor | ||
| Nov 22, 2022 at 0:03 | answer | added | John Birckhead | timeline score: 3 | |
| Nov 21, 2022 at 22:52 | history | edited | ocrdu | CC BY-SA 4.0 |
deleted 14 characters in body; edited title
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| Nov 21, 2022 at 22:00 | comment | added | Vera Fodor | @ElliotAlderson all of the GNDs will be connected through a pour. UART will be connected. | |
| Nov 21, 2022 at 21:03 | comment | added | Elliot Alderson | How are all of the other module pins connected when you want to remove power to the module? This matters very much. | |
| Nov 21, 2022 at 20:47 | history | edited | Vera Fodor | CC BY-SA 4.0 |
added 2 characters in body
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| Nov 21, 2022 at 20:26 | history | asked | Vera Fodor | CC BY-SA 4.0 |