The simulation is actually wrong. But likely the component values are not entirely well thought anyway. For an ideal 470 uF capacitor it will work, but for a real-world 470uF electrolytic capacitor with leakage current, the value is just unrealistic for real world purposes.

On a real chip, if trigger is active, i.e. low, then threshold voltage is irrelevant, and the output is always high, and disharge pin will be always off. It means that trigger pin overrides the discharge pin.

The point is, don't keep trigger pin low.

It would not work in real life either, if you keep trigger low permanently. And it would likely be affected by non-idealities of real world electrolytic capacitors too, likely requiring much longer time than calculated.

The simulation is actually wrong. But likely the component values are not entirely well thought anyway. For an ideal 470 uF capacitor it will work, but for a real-world 470uF electrolytic capacitor with leakage current, the value is just unrealistic for real world purposes.

On a real chip, if trigger is active, i.e. low, then threshold voltage is irrelevant, and the output is always high, and disharge pin will be always off. It means that trigger pin overrides the discharge pin.

The point is, don't keep trigger pin low. Pulling trigger low will trigger the delay, start charging the capacitor and set output high, but trigger must be released before capacitor threshold voltage is reached.

It would not work in real life either, if you keep trigger low permanently. And it would likely be affected by non-idealities of real world electrolytic capacitors too, likely requiring much longer time than calculated.