Timeline for Triggering an SR Latch with multiple reset lines
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| May 25, 2023 at 9:42 | vote | accept | AQMS | ||
| May 24, 2023 at 23:14 | answer | added | AnalogKid | timeline score: 0 | |
| May 24, 2023 at 21:52 | comment | added | vir | To be clear: the behavior you want is for the first high input to assert its corresponding output high and leave it high until a different input goes high? What do you want to happen if the first input is high but a second input also goes high? Or if the first input goes low while the second input is still high? | |
| S May 24, 2023 at 21:34 | review | First questions | |||
| May 24, 2023 at 22:32 | |||||
| S May 24, 2023 at 21:34 | history | asked | AQMS | CC BY-SA 4.0 |