Timeline for Would this be an acceptable implementation of an OTA-based voltage regulator?
Current License: CC BY-SA 4.0
13 events
| when toggle format | what | by | license | comment | |
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| Nov 1, 2023 at 15:37 | vote | accept | Virgil_Tibbs | ||
| Nov 1, 2023 at 15:37 | comment | added | Virgil_Tibbs | I thank you very much for the time invested in this answer. I still need to broaden my knowledge of the subject before I attempt to understand the whole thing. I will probably simplify the voltage regulator to something I understand better. | |
| Nov 1, 2023 at 13:33 | comment | added | bobflux | I edited the answer to add more detail about above questions. Normally the peak in the sims wouldn't be a problem as at that frequency the output cap dominates, the feedback loop doesn't control the circuit anymore. But it has to be compatible with the output cap... | |
| Nov 1, 2023 at 10:41 | comment | added | Virgil_Tibbs | @TimWilliams The formula for $V_{o}$ was obtained by performing small signal analysis on the circuit. Could you perhaps point me in the direction of a book/ paper/ document that delves into this topic. | |
| Nov 1, 2023 at 10:16 | comment | added | Tim Williams | @Virgil_Tibbs You have the DC form; for AC, consider gain such that gm --> gm / (1+s/w_0), and similarly for beta. Junction capacitances are also a factor, and so too is stability a concern, as evidenced by the impedance peaking visible here (which may well be full oscillation in a transient simulation; it can be hard to tell from AC analysis alone). | |
| Nov 1, 2023 at 9:55 | history | edited | bobflux | CC BY-SA 4.0 |
added 1826 characters in body
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| Nov 1, 2023 at 9:43 | comment | added | Designalog | @Virgil_Tibbs shunt feedback at the output means increasing output impedance as loop gain drops => inductive behavior. | |
| Nov 1, 2023 at 8:41 | comment | added | Virgil_Tibbs | Also I am not sure I understand how the output impedance of the circuit relates to the loop transconductance. | |
| Nov 1, 2023 at 7:34 | comment | added | Virgil_Tibbs | Would this mean I need to increase the tail current of the pair substantially to obtain something closer to the ideal expression. Conversely, couldn't I analyze the regulator from the POV of the loop gain? Like it's done in this document: diva-portal.org/smash/get/diva2:1073421/FULLTEXT01.pdf#page=49 | |
| Nov 1, 2023 at 7:29 | comment | added | Virgil_Tibbs | First of all, thank you for taking the time to simulate my circuit. I understand how you obtained the dc open loop transconductance. I don't understand the part about inductive output impedance. My calculations show that: $$V_{o}=\frac{g_{m}(\beta + 1)(R_{1}+R_{2})}{1+g_{m}(\beta + 1) R_{2}}\cdot V_{ref}$$. The product $$g_{m}(\beta + 1)$$ seems to be critical. For gm larger than unity the expression should simplify to the familiar $$\left(1+\frac{R1}{R2}\right)\cdot V_{ref}$$ | |
| Nov 1, 2023 at 4:19 | comment | added | tobalt | if they insist on not using a FET and if you don't want to recommend a PNP for the compensation issues, one more interesting variation of the output transistor could be an n-type Darlington or Sziklai arrangement. | |
| Nov 1, 2023 at 1:06 | comment | added | Tim Williams | Judging the regulator's output impedance at light load is a bit disingenuous: diff pair current is equal to load current! Increasing it will increase the output's gm, giving a more favorable measure. Conversely: at all of 1mA, I'd be more than happy to call 1Ω a "good" regulator! | |
| Oct 31, 2023 at 22:23 | history | answered | bobflux | CC BY-SA 4.0 |