Timeline for Drawing a Visual Hardware Representation for VHDL Code
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
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| Nov 29, 2023 at 12:26 | vote | accept | Marco Moldenhauer | ||
| Nov 29, 2023 at 7:55 | answer | added | Matthias Schweikart | timeline score: 2 | |
| Nov 28, 2023 at 21:09 | answer | added | vivier | timeline score: 1 | |
| Nov 28, 2023 at 20:33 | history | edited | Marco Moldenhauer | CC BY-SA 4.0 |
edited title
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| Nov 28, 2023 at 20:11 | comment | added | Marcus Müller |
electronics.stackexchange.com/questions/13995/… <-- the same from verilog. You can possibly read simple VHDL nowadays directly with yosys, or you can convert using ghdl
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| Nov 28, 2023 at 19:33 | history | asked | Marco Moldenhauer | CC BY-SA 4.0 |