Timeline for Drawing a Visual Hardware Representation for VHDL Code
Current License: CC BY-SA 4.0
3 events
| when toggle format | what | by | license | comment | |
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| Nov 29, 2023 at 12:35 | comment | added | vivier | Yes that line synchronize the input signal with the clock, it is a DFF. The schematic proposed is the outside representation of your module. In reality the hardware description of p_Register will contain at least one DFF. | |
| Nov 29, 2023 at 10:51 | comment | added | Marco Moldenhauer |
Tanks a lot. Does the symbol <= from the line r_Switch_1 <= i_Switch_1; means a register? So with this line I am creating a flipflop right?
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| Nov 28, 2023 at 21:09 | history | answered | vivier | CC BY-SA 4.0 |