Skip to main content
10 events
when toggle format what by license comment
Dec 23, 2023 at 2:42 comment added richard1941 Some day in the next century there may be square wafers. But by then the individual chips will all be circular.
Dec 15, 2023 at 16:55 comment added periblepsis @Hearth The RTP unit was targeting 200 mm, though we were already thinking about the difficulties for 300 mm. And keep in mind that the ramp rates for some parts of the recipe used in the giant washing-machine size unit (for one wafer only) were at as much as 3-5 C/s. If anything will do it, that would. 100 mm was at the time "doable" without the extreme measures. 100 mm was the proof of concept size that in part justified the immense investment money that Chris secured for his 200 mm unit.
Dec 15, 2023 at 16:36 comment added Hearth @periblepsis I haven't seen the potato-chip effect personally, because most of the wafers I work with are 100 mm SiC wafers. Since these are pretty small, and I think because SiC is more rigid than Si, this doesn't appear to be a problem in my particular use case.
Dec 15, 2023 at 8:55 comment added Simon Richter Also, even inside the used dies there are unused areas, and these have to be filled up with a pattern to avoid defects. The unusable dies on the outside fulfill the same role for the inside dies, and using a different pattern would be extra effort.
Dec 15, 2023 at 8:31 comment added periblepsis @phil1008 Hopefully, perhaps this gives you an additional story to use as good segue when asking an expert, someday in the future, who may be able to then give you an informed and comprehensive answer that includes whether or not this has anything to do with why. Or you could just call up Applied Materials and ask them. (I've done as much, myself, when curious. Just a cold call.) They might enjoy putting you in touch with someone there. If you are really curious, I think it would be worth the attempt. And you might get to know someone worthwhile knowing, too!
Dec 15, 2023 at 8:25 comment added periblepsis @phil1008 But my focus at the time was on issues of the lamp-heated environment and how to observe temps, non-contact, so that closed loop controls could control 100s of lamps to keep the surface evenly heated. So I can really only speculate. (I was able to see a solution in just a few hours' listening to Chris. Not because I'm smarter. Only because he was buried in the trees. As soon as I told him what I was thinking, he was immediately "yes, that'll work!" and "I'm drilling holes tonight. I'll let you know in the AM!" And he did! It worked! Cool experience for me. And good for him, too.
Dec 15, 2023 at 8:16 comment added periblepsis @phil1008 If you don't include my name, I don't get messaged. I didn't discussed that choice with the FAB engineers. But an educated guess would be that if they didn't include the dice out to the edge, then there would be an impact to heat dissipation at the newly exposed outside dice perimeters. So yes, I have some reason to imagine this could very well be why, at least until they had evidence to the contrary, they would choose to avoid the issue entirely and simply keep the pattern going all the way to the edge.
Dec 15, 2023 at 8:01 comment added phil1008 Could something like this potato-chip problem be the real reason? If so, it might deserve to be embellished in an answer.
Dec 15, 2023 at 6:42 comment added periblepsis Edge effects are part of the picture in some cases. The edge of a wafer dissipates quite differently than the center, as I'm sure you can imagine. At G-squared with their still-research RTP (rapid thermal processing) back in the early 1990's -- a single-wafer unit designed to complete a wafer in a couple of weeks rather than several months required for boats of wafers -- used heating rates of 3-5 C per second. Wafers would "potato-chip" due to uneven heating related mostly to that edge effect. That issue was why Chris Gronet (CEO/physicist) invited me to CA. Nice answer. +1
Dec 15, 2023 at 5:19 history answered Hearth CC BY-SA 4.0