Timeline for Verilog synthesize FIR filter coefficients in correct representation
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
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| S Mar 16 at 19:41 | history | suggested | Alex | CC BY-SA 4.0 |
Add picture of working FIR and explain solution
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| Mar 16 at 10:39 | review | Suggested edits | |||
| S Mar 16 at 19:41 | |||||
| Mar 13 at 13:59 | comment | added | Im Groot |
result of (coeff * 2^23-1) will have both integer and fractional bit se we have to apply rounding to get rid of the fractional part. Now what's left will have our desired fixed point number with 0 floating bits.
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| Mar 13 at 13:12 | comment | added | Alex | Thanks for your answer. You wrote "Convert the floating-point coefficients to fixed-point format. Just multiplying each coefficient by the scaling factor" Would this represent a fixed-point format with 0 fractional bits? | |
| Mar 13 at 12:33 | history | edited | Im Groot | CC BY-SA 4.0 |
added 2 characters in body
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| Mar 13 at 12:24 | history | answered | Im Groot | CC BY-SA 4.0 |