Might help to somebody:

When you're using blocking statements that change the 'case' value for your case block, Verilog goes into the next case block according to new 'case' value and executes it.

It looks like this behavior can cause the similar problems, as the absence of break statement in case statements in programming languages, such as C.

Might help to somebody:

When you're using blocking statements that change the 'case' value for your case block, Verilog goes into the next case block according to new 'case' value and executes it.

It looks like this behavior can cause the similar problems, as the absence of break statement in case statements in programming languages, such as C.

However, if you use non-blocking statements, this problem doesn't appear.