Timeline for STM32H matrix-vector-multiply throughput
Current License: CC BY-SA 4.0
13 events
| when toggle format | what | by | license | comment | |
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| May 10 at 16:16 | comment | added | Eelco Hoogendoorn | Thanks; that sections seems to pertain to the 16bit int signal processing functionality... but at least it goes into some detail and if the hardware support for that is better its certainly concievable to quantize my matrices as such, rather than using the f32 fmad. | |
| May 10 at 14:18 | comment | added | user1850479 | @EelcoHoogendoorn The description in the datasheet is brief because the memory controller is documented in the reference manual. See page 797 onwards. | |
| May 10 at 6:37 | comment | added | Eelco Hoogendoorn | @user1850479 the first page of the datasheet also isnt quite that explicit; the way I read the sentence/punctuation is that that 100mhz refers to the speed of the flash; but the meagre section dedicated to elaborating on the memory systems does not infact elaborate. Infact it might win the 'all time record for introducing more terms in a single page without explaining a single one of them' award. | |
| May 10 at 6:32 | comment | added | Eelco Hoogendoorn | Thanks. Those high level numbers may or may not correspond to anything you care about n reality though; not quite sure which speed that refers to. But if its to be taken as an absolute maximum for anything happening to ram at all, it means that a copy from ram to TCM would run at 5.5 core cycles per 32bit value moved? Its not great; but acceptable for my purposes I guess. That said ive seen somewhere that DMA only runs at some fraction of the max bus speed, so reality might be more disappointing still. | |
| May 10 at 4:37 | answer | added | Theoristos | timeline score: 0 | |
| May 10 at 0:56 | answer | added | Kuba hasn't forgotten Monica | timeline score: 0 | |
| May 9 at 23:38 | comment | added | user1850479 | The first page of the STM32H743x datasheet says it has a 32 bit, 100 MHz memory bus. DMA performance will depend on what memory you connect to that bus, but you certainly won't copy faster than the bus can run. | |
| May 9 at 20:48 | comment | added | Eelco Hoogendoorn | Its interesting I cannot even find figures on simpler questions like DMA ram-ram copy bandwidth. What I can find from lower-end stm32 models its looking kinda scary; on high power cpus you expect DMA to be an order of magnitude faster than the CPU could consume it, but what im seeing from these low end STM DMA controllers you are lucky to get one byte per 10 cpu cycles... which wouldnt be the answer I was hoping for. | |
| May 9 at 20:34 | comment | added | Eelco Hoogendoorn | I think ive been pretty explicit about the vector operation in question no? 128-element f32 matrix-vector multiplies. If I can do about 10k of those a second im happy. Then there are a million other things that go into my chip selection. Might make another question about that; but I really dont want to pull that in scope here. | |
| May 9 at 20:14 | comment | added | Eelco Hoogendoorn | Well... in actuality this is a research issue very early in the project; just trying to avoid dragging chip selection into this discussion, and learn more about what I can expect compute-wise from STM32 chips. | |
| May 9 at 20:12 | comment | added | periblepsis | If this is for a commercial board where the vector throughput is a core function to the application, then wouldn't this have been promoted to a research issue to be resolved very early in the project? I think your question is good! Don't get me wrong. But when I read that you "be working with a board that has a STM32H743 on it", which means that decision is already taken, then I wonder about the early design process that didn't resolve this question by the time someone is moving forward with board design. Seems like the cart before the horse. What's going on? Or is this a personal project? | |
| S May 9 at 19:13 | review | First questions | |||
| May 10 at 4:37 | |||||
| S May 9 at 19:13 | history | asked | Eelco Hoogendoorn | CC BY-SA 4.0 |