Technically, a compiler would have to treat P2.2 and P2.5 as volatile bit-valued variables (that are aliased into and with the volatile byte-valued variable P2), since the read and write operations on them may be entirely different operations, unconnected to one another; and P2 is associated with external pins on the CPU. So, it depends on how it's set up in the circuit containing the CPU.
Port 2 function is time-multiplexed as address bits 8-15 of the 16-bit address bus along with bi-directional I/O (address bits 0-7 go out through port 0, i.e. P0). This is seen here Internal architecture of the 8051 Ports 0, 1, 2 and 3 in further detail. I don't exactly remember what it is, but I'm pretty sure that there is also an external pin made available for the circuit to use to determine when P0 and P2 are in address-bus mode versus bi-directional I/O mode. For bi-directional I/O operations, the inputs and outputs are separately latched. That is the sense in which reads and writes on P2 are independent.
Apart from timing (which may actually be relevant), the operations you specified are equivalent to the sequence:
write 1 to CY
read P2.2, then write 1 to P2.2
write 0 to CY
read P2.5, then write 0 to P2.5
What the read operations actually do depends entirely on how the circuit is set up. Reads might do things in the circuit, even if the values read aren't being used by the CPU. These are the same kinds of issues that you encounter when dealing with volatile variables in C or C++.