Timeline for VHDL: is this RAM design over-complicated?
Current License: CC BY-SA 4.0
14 events
| when toggle format | what | by | license | comment | |
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| Aug 4 at 0:22 | comment | added | Dave Tweed | You might want to check out Yosys. I believe it can target a fairly generic set of logic primitives for abstract synthesis. | |
| Aug 3 at 22:20 | comment | added | wbs2422 | @Kubahasn'tforgottenMonica oh right ! now I'm starting to understand why my design is unefficient : I'm wasting a lot of FPGA resources because I have to use full blocks even if I'm actually using "1%" of its power ... My big mistake was to think like if it was a software and not a digital circuit. Do you know if there is a tool which can synthesis the HDL like if it were to be implemented as an ASIC tailored for the given application ? | |
| Aug 3 at 22:02 | comment | added | wbs2422 | @DaveTweed my question became a mess, I fully rewrote it to make it cleaner, sorry for the inconvenience | |
| Aug 3 at 21:27 | comment | added | Kuba hasn't forgotten Monica | @Wheatley FPGAs are rather ill equipped to synthesize RAM. So it will always look overly complicated because an FPGA simply does not have the building blocks needed to efficiently synthesize RAM. If you were building that RAM using physical logic chips (say CD4000 series), it would have been quite a bit simpler than what the FPGA synthesis tool spat out. For one thing, you could do pseudo-SRAM as self-refreshing DRAM, with very little logic needed. | |
| Aug 3 at 19:44 | comment | added | wbs2422 | sorry I didn't realized that my question was somehow unclear, I'll add my goal in it. Mainly: understanding how to design a RAM from scratch to understand how it works (this RAM will be used in the design of a CPU that I'm currently working on for learning purposes). Being able to make it work in simulation is enough for me, I do not intend to implement it in a FPGA. | |
| Aug 3 at 19:39 | comment | added | Dave Tweed | If it works for you, that's fine. But I've completely lost the thread in terms of what you're looking for. Your question is all about FPGA synthesis results, but in other comments, you say you're more interested in RAM in a more abstract sense, and simulation. So I have no idea where to go with this. SRAM in general, including the block RAM found in FPGAs, works in ways that are not readily described by purely logical functions. | |
| Aug 3 at 17:29 | comment | added | wbs2422 | as I suspected this issue was resolved by using variables in a process. With this code I got results similar to those I've got with the original design. Perhaps they are inherent to a RAM design and should be expected instead of considered as "over-complicated" like I did. I tried a new design and it happens that the synthesis mapped it to RAM blocks, that is probably much more efficient for a practical implementation on a FPGA. But my goal was to understand what's inside these RAM blocks and to design one from scratch... I put the design and info in a new edit. What do you think ? | |
| Aug 2 at 22:40 | comment | added | wbs2422 | I am getting simulation issues "A fatal run-time error was detected. Simulation cannot continue.". Running it step-by-step shows that it's triggered on the very first access to the memory. I suspect it comes from an unexpected init value of the index signal. I had this issue previously, the init value of the index signal was negative, hence the test (index < DATA_RAM_MEMORY_SIZE) passed and the module tried to read an unexisting location. I solved it by changing signals to variable, it's why I had to use a process also for the reading. I'll investigate tomorrow and let you know. Thanks | |
| Aug 2 at 21:39 | comment | added | Dave Tweed | And BTW, note that I did away with the global reset. Having that guarantees that you cannot use BRAM for the memory array. | |
| Aug 2 at 21:37 | comment | added | Dave Tweed | See edit above. | |
| Aug 2 at 21:36 | history | edited | Dave Tweed | CC BY-SA 4.0 |
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| Aug 2 at 19:40 | comment | added | wbs2422 | Thank you for your code suggestion. Here we write the entire data_in signal. Is there a way to add byte and halfword writings ? I've been thinking about concatenation: let's take as an example the writing of a byte at the 3rd location of the word: memory(index) <= memory(index)(31 downto 24) & data_in(23 downto 16) & memory(index)(15 downto 0) | |
| Aug 2 at 18:22 | history | edited | Dave Tweed | CC BY-SA 4.0 |
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| Aug 2 at 12:20 | history | answered | Dave Tweed | CC BY-SA 4.0 |