Timeline for How to define a function in Verilog?
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
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| Aug 13 at 21:25 | comment | added | CLAUDE | Such a cool trick! Thanks for sharing | |
| Aug 13 at 21:13 | comment | added | Tom Carpenter | @CLAUDE there's also a clever example here for parameterising a function by wrapping it in a module. | |
| Aug 13 at 20:59 | comment | added | Tom Carpenter | @CLAUDE You can use parameters for the widths. But when passing values in (even constants) as inputs to the function, they stop being parameters and instead become variables. | |
| Aug 13 at 20:58 | history | edited | Tom Carpenter | CC BY-SA 4.0 |
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| Aug 13 at 20:57 | comment | added | CLAUDE | Thanks for your response. It is interesting that verilog does not admit a parameterized vector length. | |
| Aug 13 at 20:56 | vote | accept | CLAUDE | ||
| Aug 13 at 20:52 | history | edited | Tom Carpenter | CC BY-SA 4.0 |
added 798 characters in body
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| Aug 13 at 20:46 | history | edited | Tom Carpenter | CC BY-SA 4.0 |
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| Aug 13 at 20:39 | history | answered | Tom Carpenter | CC BY-SA 4.0 |