Timeline for Why remove load resistance for DC analysis in transistor amp?
Current License: CC BY-SA 4.0
12 events
| when toggle format | what | by | license | comment | |
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| Nov 11 at 10:09 | vote | accept | Yeslin Sequeira | ||
| Nov 11 at 8:59 | history | edited | SamGibson♦ | CC BY-SA 4.0 |
Added line breaks (2 x space at EOL) in the reference text, so it displays as intended (as per Markdown syntax)
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| Nov 11 at 8:56 | history | edited | Yeslin Sequeira | CC BY-SA 4.0 |
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| Nov 11 at 8:51 | history | edited | Yeslin Sequeira | CC BY-SA 4.0 |
added 64 characters in body
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| Nov 11 at 8:49 | answer | added | Andy aka | timeline score: 1 | |
| Nov 11 at 8:46 | history | edited | Yeslin Sequeira | CC BY-SA 4.0 |
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| Nov 11 at 8:36 | comment | added | Yeslin Sequeira | @Andy the textbook recommends halfway between Vdd & ground, because apparently, that's where the slope of the Vout vs Vbias curve is the highest, so small signal gain is the highest. But that curve is in open circuit conditions, I don't understand how it relates to when R_L is present | |
| Nov 11 at 8:33 | comment | added | Yeslin Sequeira | @a360pilot How can I get a thevenin equivalent of a non-linear device? Isn't thevenin applicable in only linear networks? | |
| Nov 11 at 8:31 | comment | added | Andy aka | What output load voltage do you want to have when the input signal is zero. | |
| Nov 11 at 8:28 | comment | added | a360pilot | Think about the Thevenin equivalent of this circuit. Let's say you were to represent it with a voltage source in series with a resistor. How would you go about calculating that voltage? | |
| S Nov 11 at 8:17 | review | First questions | |||
| Nov 11 at 8:58 | |||||
| S Nov 11 at 8:17 | history | asked | Yeslin Sequeira | CC BY-SA 4.0 |