Timeline for How would a 4-bit full-adder be implemented in a Cyclone V FPGA?
Current License: CC BY-SA 4.0
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| when toggle format | what | by | license | comment | |
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| 19 hours ago | comment | added | greybeard | "You can of course add two 4-bit numbers in a single clock cycle [combinatorically]" (or "single level" of delay) This necessitates two 9-input LUTs for sum MSB and carry out. | |
| yesterday | comment | added | shafe | I think I see what you're saying. In the above diagram where there's only 1 arrow leading from the adaptive LUT to either adder, there really are 2 bits going to each full adder (4 bits total) then correct? And the adders combine the combinatorial outputs with the carry bits? | |
| yesterday | history | answered | Marcus Müller | CC BY-SA 4.0 |