I've edited my answer to show the circuit diagram with more detail and also cover the questions in the coments from David Kessner and Vasiliy Zukanov: -

Two gates are used; the OR gate has to be zero before a timer clocked with what I've called "super-clock" is primed. Once it is primed it then starts counting as soon as either CLK1, CLK2 or both go high.

It finishes timing as soon as a zero is detected on the output of the EXOR gate.

Super-clock is a clock running significantly higher than CLK1 or CLK2. If the timer doesn't count to anything after being primed and triggered it is because the positive edge time difference between CLK1 and CLK2 is insignificant.

I've edited my answer to show the circuit diagram with more detail and also cover the questions in the comments from David Kessner and Vasiliy Zukanov: -

Two gates are used; the OR gate has to be zero before a timer clocked with what I've called "super-clock" is primed. Once it is primed it then starts counting as soon as either CLK1, CLK2 or both go high.

It finishes timing as soon as a zero is detected on the output of the EXOR gate.

2nd EDIT to provide information that is a little clearer.

Super-clock is a clock running significantly higher than CLK1 or CLK2. The period of super-clock is many times smaller than the period of either CLK1 or CLK2. 

If the timer doesn't count to anything after being primed and triggered it is because the positive edge time difference between CLK1 and CLK2 is insignificant.

If it counts to 1 and no more then it can be assumed that the time delay between CLK1 and CLK2 is between zero and one-super-clock period i.e. it is still insignificant. If it counts to two or higher than this can be arbitrarily taken as the two clocks not rising synchronously.

It sounds easy and so does my proposal for a solution but there's subtlety somewhere that I've probably missed. Here's the basic idea: -

When clk1 and clk2 are both at zero, this is the point at which the timer may be primed to start counting. This needs a OR gate (not shown) to be used. The timer is primed and as soon as one clock rises this creates a logic high on the output of the exclusive or gate. At this point a timer is started.

When the next clock rises the output from the ex-or goes to zero and the timer is halted.

This circuit can time the difference between two positive rising edges on two lines.

But there is a problem... if the two clocks rise at exactly the same time, the ex-or never reaches 1 and therefore the OR gate (previously mentioned) is required to trigger the timer and if the output from the ex-or is zero immediately afterwards, the timer counts zero to indicate that the clocks were as close in rising as were possible to detect.

I've edited my answer to show the circuit diagram with more detail and also cover the questions in the coments from David Kessner and Vasiliy Zukanov: -

Two gates are used; the OR gate has to be zero before a timer clocked with what I've called "super-clock" is primed. Once it is primed it then starts counting as soon as either CLK1, CLK2 or both go high.

It finishes timing as soon as a zero is detected on the output of the EXOR gate.

Super-clock is a clock running significantly higher than CLK1 or CLK2. If the timer doesn't count to anything after being primed and triggered it is because the positive edge time difference between CLK1 and CLK2 is insignificant.