Timeline for Detection of simultaneous edges of two asynchronous clocks
Current License: CC BY-SA 3.0
15 events
| when toggle format | what | by | license | comment | |
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| Jun 23, 2013 at 16:20 | history | edited | Andy aka | CC BY-SA 3.0 |
a little more clearer info
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| Jun 22, 2013 at 10:29 | comment | added | Andy aka | @VasiliyZukanov I'm not sure what I need to do. The way I see it working is that if the "super" count is zero when the ex-or is zero then the two clocks had rising edges that occured simultaneously (within one super-clock time period). I'm not a digital expert and I don't understand about possible metastable states of the timer I may have assumed. | |
| Jun 22, 2013 at 6:55 | comment | added | Vasiliy | @ Andy aka, furthermore, I believe that the outputs of the gates you've shown need to be synchronized to "super-clock" clock domain. Otherwise, what assumptions about possible metastable states of the timer have you made? | |
| Jun 22, 2013 at 6:34 | comment | added | Vasiliy | @ Andy aka, you meant to say that the time period is much shorter, right? I still can't grasp the whole picture of the solution you propose. I'm familiar (basically) with the theory of PLLs, but I can't see how the output of PLL's phase detector may be directly fed into digital logic without causing metastability issues. I'm sure that if you'll put a complete schematic diagram of the solution it will be much easier to discuss it. | |
| Jun 21, 2013 at 21:45 | history | edited | Andy aka | CC BY-SA 3.0 |
deleted 298 characters in body
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| Jun 21, 2013 at 21:33 | comment | added | Andy aka | @Vasiliy the timer starts when the OR gate goes high i.e. both clocks are low and one (or the other, or both) rises high. I'm no digital expert so maybe I'm missing something. I'll try a better circuit diagram. | |
| Jun 21, 2013 at 21:31 | comment | added | Andy aka | @Vasiliy I'm assuming the super-clock time period is significantly higher than either clk1 or 2 and that if it doesn't count anything when the pre-conditions are met, this is the measure of the two clocks rising simultaneously (within one time measure of the super-clock). | |
| Jun 21, 2013 at 21:28 | comment | added | Andy aka | @DavidKessner yeah I was basing it on the ADF4111 frequency phase detector analog.com/static/imported-files/data_sheets/… | |
| Jun 21, 2013 at 20:40 | comment | added | user3624 | @Andyaka What you describe is actually closer to this kind of phase-frequency detector commonly used in PLL's. Here'a a link to a diagram: 2.imimg.com/data2/JR/GW/MY-719802/a-250x250.jpg | |
| Jun 21, 2013 at 20:35 | comment | added | Vasiliy | Your "super-clock" can't be synchronous to both input clocks because they are asynchronous, therefore, no matter what do you mean by "super-clock", the metastability issue remains. Maybe I'm missing some major point in your idea? Can you add schematic of the complete circuit? BTW, your timer will be enabled also when one of the clocks goes low while the other is still high. | |
| Jun 21, 2013 at 20:16 | comment | added | Andy aka | @Vasiliy The timer I referred to is ill-defined but I didn't assume it would be clocked from one of the two clocks but rather from some arbitrarily high super-clock that was able to "measure" the time difference. If this isn't allowed then please modify the question. | |
| Jun 21, 2013 at 20:13 | comment | added | Andy aka | @DavidKessner the condition for starting the timer have to be met and that is both clocks have to be at zero to prime the circuit. Shouldn't that mean that the circuit doesn't care that they may be of different frequencies? I may be wrong about that of course but i was just trying to measure the point at which both clocks were at zero to prime the timer circuit. | |
| Jun 21, 2013 at 20:06 | comment | added | Vasiliy | When you say "timer" you're probably referring to some circuit containing flops. With what clock are these flops clocked? Use either one of two clocks in question, you're still getting metastability issue in timer. Doesn't seem like a good solution. | |
| Jun 21, 2013 at 19:53 | comment | added | user3624 | This doesn't work if the two clocks are different frequencies or different duty cycles. | |
| Jun 21, 2013 at 19:51 | history | answered | Andy aka | CC BY-SA 3.0 |
