Timeline for Verilog - variable number of inputs/outputs
Current License: CC BY-SA 3.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jul 16, 2013 at 7:14 | comment | added | travisbartley | @ballaw, generate statements are generally synthesizeable. | |
| Jul 16, 2013 at 5:39 | comment | added | ballaw | Thanks for the answer. Are generates synthesizable, though? | |
| Jul 16, 2013 at 5:39 | vote | accept | ballaw | ||
| Jul 16, 2013 at 2:30 | comment | added | travisbartley | This is the right answer, but its also worth noting that a define statement can be used as well. I prefer to use parameter when the constant is used in only the local file and I use define when the constant spans multiple files. But it is up to the designer's discretion. | |
| Jul 16, 2013 at 2:11 | history | answered | Greg | CC BY-SA 3.0 |