Timeline for Assign binary in VHDL
Current License: CC BY-SA 3.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 19, 2013 at 14:45 | history | edited | Gustavo Litovsky | CC BY-SA 3.0 |
edited title
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| Sep 19, 2013 at 8:36 | answer | added | MiljanNC | timeline score: 1 | |
| Sep 19, 2013 at 8:32 | answer | added | user16324 | timeline score: 2 | |
| Sep 19, 2013 at 0:17 | comment | added | user8352 | I'd suspect revealing just a bit more might be helpful. Constructing a simple testcase with an architecture declarative item for data0_sim and a concurrent signal assignment statement as shown yields no obvious errors, meaning more context appears needed. The actual error message might help, noting there can be errors that don't point to the character or line position where the actual syntax problem is found. | |
| Sep 18, 2013 at 21:47 | history | asked | Ross W | CC BY-SA 3.0 |